1. Field of the Invention
The present invention relates to a logic simulator for verifying circuit operating characteristics of a logic circuit including MOS transistors.
2. Description of the Background Art
FIG. 19 is a block diagram of a conventional logic simulator for a logic circuit including MOS transistors. FIGS. 20 to 23 are flow charts of the verification of the circuit operating characteristics by the logic simulator of FIG. 19.
The verification of the circuit operating characteristics by the logic simulator of FIG. 19 will be described hereinafter with reference to FIGS. 20 to 23.
A circuit connection data providing means not shown applies to an event generator 102 a circuit connection data D1 which specifies circuit connections in the logic circuit to be simulated in the step S101. An input pattern signal providing portion 101 applies to the event generator 102 an input pattern signal D2 which becomes a test pattern in the step S102.
In the step S103, the event generator 102 generates a signal value change (or an event) as a function of the input pattern signal D2 in signal lines in the logic circuit which are specified by the circuit connection data D1, to output a circuit connection data D3 with event information to an MOST (transistor) input signal extractor 103.
In the step S104, the MOST input signal extractor 103 extracts an MOS transistor having an input terminal (drain or source) connected to a wiring (or a net) in which the event is generated from the circuit connection data D3 while recognizing the conductivity type of the MOS transistor. The MOST input signal extractor 103 also extracts signal values applied to the input and gate terminals of the MOS transistor, to output a circuit connection data D4 with MOS input information to an MOST output signal determiner 104.
In the step S105, the MOST output signal determiner 104 determines an output signal value which appears at the output terminal (drain or source) of the MOS transistor as a function of the circuit connection data D4, to output a circuit connection data D5 with MOS output information to an on-net signal value processor 105. The determination will be described below with reference to FIG. 21.
The MOS (conductivity) type of the MOS transistor having the input terminal at which the event is generated (hereinafter referred to as an "event generation MOST") is identified in the step S111. The process proceeds to the step S112 when the MOS type is P, and the process proceeds to the step S113 when the MOS type is N.
A gate signal value of the P type event generation MOST is judged in the step S112. The process proceeds to the step S114 when the gate signal value is at high impedance (Z) or indefinite (X). The process proceeds to the step S115 when the gate signal value is "1" (at H level), and proceeds to the step S117 when it is "0" (at L level). At the same time, a gate signal value of the N type event generation MOST is judged in the step S113. The process proceeds to the step S116 when the gate signal value is at high impedance (Z) or indefinite (X). The process proceeds to the step S115 when the gate signal value is "0", and proceeds to the step S117 when it is "1".
In the steps S114 and S116, the ON/OFF state of the event generation MOST is regarded as indefinite, so that an indefinite signal X is outputted. In the step S115, the event generation MOST is regarded as OFF, so that a high-impedance signal Z is outputted. In the step S117, the event generation MOST is regarded as ON, the input signal is outputted as it is.
After the output signal value of the event generation MOST is determined in one of the steps S114 to S117, the process proceeds to the step S106 of FIG. 20.
In the step S106 of FIG. 20, the on-net signal value processor 105 determines the signal values of a net which is in a signal competing condition from the circuit connection data D5, to output a net-processed circuit connection data D6 to a simulation time controller 106. The net processing is described below with reference to FIG. 22.
It is detected in the step S121 whether or not the net to which the output signal of the event generation MOST is applied is in the signal competing condition. The process proceeds to the step S122 when it is in the signal competing condition, and the process proceeds to the step S123 when it is not.
In the step S122, the value of a signal having the maximum signal strength among a plurality of signals which compete with each other is determined as a net signal value. The process then proceeds to the step S107 of FIG. 20. The signal strength denotes a drive capability of the transistors composing the logic circuit as a function of transistor size.
In the step S123, since the net connected to the output signal of the event generation MOST is not in the signal competing condition, the output signal value of the event generation MOST is determined intactly as the net signal value. The process then proceeds to the step S107 of FIG. 20.
The simulation time controller 106 carries out a simulation time control processing as a function of the net-processed circuit connection data D6 in the step S107 of FIG. 20. When it is necessary to continue the simulation, the simulation time controller 106 outputs a circuit connection data D7 with simulation time to the event generator 102 to instruct to continue the simulation. When it is judged that the simulation is completed, the process proceeds to the step S108 of FIG. 20. The simulation time control processing will be described below with reference to FIG. 23.
It is checked whether or not the event generation is completed at the current simulation time. When it is judged that the event generation is not completed, the process proceeds to the step S103 of FIG. 20 to continue the simulation without changing the simulation time.
When it is judged that the event generation is completed in the step S125, the process proceeds to the step S126. It is checked in the step S126 whether or not the simulation time is a (simulation) finish time. When it is, the process proceeds to the step S108 of FIG. 20 to complete the simulation.
When it is not, the simulation time is put forward in the step S127. The process then proceeds to the step S103 of FIG. 20 so that the event generator 102 generates a new event with the renewed simulation time to continue the simulation.
The process returns to the step S103 when it is judged to continue the simulation in the step S107 of FIG. 20. The event generation, extraction of the input signal of the MOST, determination of the output signal of the MOST, on-net signal value processing and simulation time control processing are continued as a function of the circuit connection data D7 in the steps S103 to S107, until the completion of the simulation is recognized in the step S107.
The process proceeds to the step S108 when it is judged in the step S107 that the simulation is completed. In the step S108, an simulation result output means not shown outputs to a CRT not shown or the like a simulation result list including signal names, event generation time, signal values and the like as a function of a circuit connection data D8 with whole event information.
FIG. 28 is a block diagram of a conventional logic simulator in which the signal strength is taken into consideration. Reference numeral 201 designates a circuit connection data storing portion provided in a computer and for storing a circuit connection data a equivalent to the logic circuit; 202 designates a signal strength data providing portion for setting, to the circuit connection data a, a signal strength data serving as relative representation of electrical charge providing capability for the logic simulation; 203 designates a logic simulation executing portion at plural signal strength level which is capable of handling the signal strength data; 204 designates a simulation result output portion for outputting the execution result of the logic simulation to a CRT, printer or the like; 205 designates a circuit constant data providing portion for setting a circuit constant value for circuit simulation to the circuit connection data a; 206 designates a circuit simulation executing portion which is capable of handling the circuit constant; and 207 designates a simulation result output portion for outputting the execution result of the circuit simulation to the CRT, printer or the like.
The function of the prior art will be discussed hereinafter with reference to FIGS. 28, 29 and 30.
FIG. 29 is a circuit diagram of an exemplary circuit connection data for logic circuit simulation. Reference numeral 108 designates an inverter logic element model; 109 designates a tri state buffer element model for outputting logical signals 1, 0 and high impedance; 110 designates a data input signal line for the tri state buffer 109; 111 designates an input signal line for controlling data transmission (1 and 0 outputs) or non-transmission (high impedance) for the tri state buffer 109; 112 designates an NMOS transistor element model; 113 designates a forced reset input signal line connected to the gate terminal of the NMOS transistor 112; 114 designates a ground element model connected to the source terminal of the NMOS transistor 112; 115 designates a signal line which causes signal value competition; 116 designates an inverter logic element model; and 117 designates an output signal line of a data latch circuit with reset function which includes the foregoing element models. FIG. 30 shows a logical construction of the tri state buffer 109. Reference character 118a designates a power supply terminal; and 118b designates earth.
The function of the conventional logic simulator on the circuit connection data shown in FIGS. 29 and 30 will be described below. A circuit designer manually sets the signal strength data required to operate the circuit to the respective element models composing the circuit by means of the signal strength data providing portion 202 of FIG. 28. That is, he sets a low strength level (weak) to the inverter 108, a medium strength level (medium) to the tri state buffer 109, and a high strength level (strong) to the NMOS transistor 112. An input signal is applied to the circuit connection data to which the signal strength data are applied, whereby the logic simulation executing portion 203 executes the logic simulation. The simulation result output portion 204 outputs the result of the simulation to verify the circuit design at a logical level.
For design verification at a circuit level, the circuit constant value is set to the circuit connection data a by means of the circuit constant data providing portion 205. Channel length L.sub.p1 and channel width W.sub.p1 of a PMOS transistor and channel length L.sub.n1 and channel width W.sub.n1 of an NMOS transistor are set to the inverter 108 of FIG. 29. Channel length L.sub.p2 and channel width W.sub.p2 of the PMOS transistor and channel length L.sub.n2 and channel width W.sub.n2 of the NMOS transistor are set to the tri state buffer 109. Channel length L.sub.n3 and channel width W.sub.n3 of the NMOS transistor are set to the NMOS transistor 112. Channel length L.sub.p4 and channel width W.sub.p4 of the PMOS transistor and channel length L.sub.n4 and channel width W.sub.n4 of the NMOS transistor are set to the inverter 116.
Next, the input signal is applied to the circuit connection data to which the circuit constant data are applied, whereby the circuit simulation executing portion 206 of FIG. 28 executes the circuit simulation. The simulation result output portion 207 outputs the result of the simulation, so that the circuit design is verified at the circuit level.
The conventional logic simulator of FIG. 19 for the logic circuit including the MOS transistors is constructed as above mentioned. The output signal of the event generation MOST is determined on the MOS type, input signal value and gate signal value in the conventional logic simulator, as shown in the flow chart Of FIG. 21.
The output signal of the MOS transistor has the signal strength which is fixed depending on the transistor size. Disadvantageously, the signal transmitting characteristics of the MOS transistor, i.e., dynamic change in ON-resistance with the input signal value is not taken into consideration for the signal strength verification.
The signal level (or voltage level) of the output signal is insufficient in some cases where the ON-resistance of the MOS transistor is outputted in a relatively high resistive condition. The MOS transistor having the gate input of the insufficient voltage might not be turned off when it should be, resulting in a through current (source to ground current) flow. A through current means a current flowing from source to ground through a transistor insufficiently turned off. There arises a problem that the presence/absence of the danger that the through current is produced is not taken into consideration for the simulation.
In the conventional logic simulator, a state transition delay time between the appearances of the input and output signals of the MOS transistor is not taken into account at all. If considered, the state transition delay time is fixed in the simulation. This causes a problem that the state transition delay time of the input and output signals of the MOS transistor is not correctly calculated for the simulation.
The conventional logic simulator in which the signal strength is taken into consideration is constructed as shown in FIG. 28. For the design verification of the logic circuit by means of the logic simulation and circuit simulation, it is necessary to manually apply, to the circuit connection data a, the signal strength for the logic simulation and the circuit constant for the circuit simulation as circuit informations separately for the respective simulation systems. A large amount of manual work is required. Since the relation between the signal strength and circuit constant is not verified, the circuit operation is not ensured for the practical device in the logic simulation. Since a large amount of information is applied to the circuit connection data, a large amount of data must be stored.